ARM64 System Emulator

Simulating a real processor at cycle-level accuracy requires faithfully modeling every pipeline stage, hazard condition, and cache policy — not just the instruction set.

A cycle-accurate emulator in C covering ALU, register file, and memory, extended with a 5-stage instruction pipeline implementing hazard detection, branch prediction, and register forwarding, plus an L1 data cache with LRU replacement and configurable associativity and block size.

65% reduction in execution time over a single-stage baseline; L1 cache hitting 90%+ with tuned associativity and block size configurations.